Title :
Low-area, pipelined conversion from signed-binary, to two´s-complement, number representation
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
fDate :
9/26/1996 12:00:00 AM
Abstract :
A new architecture is proposed for the conversion of numbers from signed-binary to two´s-complement representation, where the former arrives in a skewed, most-significant-digits-first format, due to pipelined arithmetic operations
Keywords :
computer architecture; integrated logic circuits; pipeline arithmetic; low-area implementation; pipelined arithmetic operations; pipelined conversion; signed-binary number representation; skewed most-significant-digits-first format; two´s-complement number representation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19961257
