Title :
ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology
Author :
Wang, Chang-Tzu ; Ker, Ming-Dou
Author_Institution :
Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao Tung Univ. (NCTU), Hsinchu, Taiwan
Abstract :
An electrostatic discharge (ESD) protection design for smart power applications with lateral double-diffused MOS (LDMOS) transistors is investigated. With the gate-driven and substrate-triggered circuit techniques, the n-channel LDMOS can be quickly turned on to protect the output drivers during an ESD stress event. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-μm 5 V/40 V bipolar CMOS DMOS (BCD) process, which can sustain ESD voltages of 4 kV in human-body-model (HBM) and 275 V in machine-model (MM) ESD tests. In addition, the power-rail ESD protection design can also be achieved with a stacked structure to protect 40-V power pins without a latchup issue in the smart power integrated circuits.
Keywords :
CMOS integrated circuits; MOSFET; electrostatic discharge; ESD stress event; bipolar CMOS DMOS process; electrostatic discharge protection design; gate-driven circuit technique; human-body-model; lateral double-diffused MOS transistors; machine-model ESD tests; n-channel LDMOS; output drivers; power-rail ESD protection; size 0.35 mum; smart power applications; smart power integrated circuits; stacked structure; substrate-triggered circuit technique; voltage 275 V; voltage 40 V; voltage 5 V; Bipolar transistors; Driver circuits; Electrostatic discharge; MOSFETs; Stress; Substrates; Bipolar CMOS DMOS (BCD) process; ESD protection; electrostatic discharge (ESD); latchup;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2010.2079530
