Circuit and architecture trade-offs for high-speed multiplication

Author

Song, Paul J. ; De Micheli, Giovanni

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

26

Issue

9

fYear

1991

fDate

9/1/1991 12:00:00 AM

Firstpage

1184

Lastpage

1198

Abstract

VLSI implementations of high-performance parallel multipliers are discussed. Circuit building blocks required for partial-product reduction are analyzed and two schemes leading to highly regular layouts are proposed. The circuit implementations related to the first-scheme in three different BiCMOS technologies are discussed. The die size and performance for nominal design rule values are compared, and the trend in scaling the feature sizes is studied. A silicon implementation of a prototype slice of an IEEE double-precision floating point multiplier in a 0.8-μm double-metal BiCMOS technology is presented

Keywords

BIMOS integrated circuits; VLSI; digital arithmetic; integrated logic circuits; logic design; parallel processing; 0.8 micron; BiCMOS technologies; IEEE double-precision; VLSI implementations; counters; die size; double metal technology; feature sizes; floating point multiplier; high-speed multiplication; highly regular layouts; nominal design rule values; parallel multipliers; partial-product reduction; prototype slice; scaling; Adders; BiCMOS integrated circuits; CMOS technology; Circuit analysis; Circuit synthesis; Circuit testing; Counting circuits; Senior members; Silicon; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.84935

Filename

84935