Yield optimization in large RAM´s with hierarchical redundancy

Author

Ganapathy, Kumar N. ; Singh, Adit D. ; Pradhan, Dhiraj K.

Author_Institution

Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA

Volume

26

Issue

9

fYear

1991

fDate

9/1/1991 12:00:00 AM

Firstpage

1259

Lastpage

1264

Abstract

The authors present and analyze large RAM architectures with hierarchical redundancy and determine the optimal redundancy organization for yield enhancement. A two-level redundancy scheme is used for defect tolerance, and the defect distribution is modeled using the compounded Poisson model. The tree random access memory (TRAM), which has been proposed as a design methodology for future multimegabit memories (N. Jarwala et al., 1988) is considered as an example for modeling and optimization. The results show that the two-level hierarchical redundancy approach, with spare bit and word lines within memory quadrants, and additional spare modules for global sparing, along with redundant interconnections can efficiently provide defect tolerance and viable yields for future generations of high-density dynamic random access memories

Keywords

DRAM chips; memory architecture; redundancy; statistical analysis; TRAM; compounded Poisson model; defect tolerance; design methodology; dynamic random access memories; hierarchical redundancy; high density DRAM; large RAM architectures; multimegabit memories; optimal redundancy organization; tree random access memory; two-level redundancy scheme; yield enhancement; Circuit faults; DH-HEMTs; Design optimization; Integrated circuit yield; Memory architecture; Prototypes; Random access memory; Read-write memory; Redundancy; Semiconductor device modeling;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.84942

Filename

84942