Title :
Variable-taper CMOS buffers
Author :
Vemuru, Srinivasa R ; Thorbjornsen, Arthur R.
Author_Institution :
Dept. of Electr. Eng., Toledo Univ., OH, USA
fDate :
9/1/1991 12:00:00 AM
Abstract :
A variable-taper (VT) approach to buffer design in which the taper from one inverter stage to the next is a function of the position of the inverter within the buffer chain is proposed. Though the minimum delay obtained by using a VT buffer is about 15% more than the minimum delay obtained from conventional fixed-taper (FT) buffers, a small modification to the initial stages of the VT buffer reduces this difference to less than 2%. For similar delays, a VT buffer usually takes less area and consumes less power than an FT buffer
Keywords :
CMOS integrated circuits; buffer circuits; integrated logic circuits; logic design; CMOS buffers; buffer design; inverter stage; minimum delay; variable-taper; Capacitance; Delay effects; Delay estimation; Inverters; Logic circuits; Logic devices; Logic gates; Power dissipation; Propagation delay;
Journal_Title :
Solid-State Circuits, IEEE Journal of
