DocumentCode
1353391
Title
Latched CMOS differential logic (LCDL) for complex high-speed VLSI
Author
Wu, Chung-Yu ; Cheng, Kuo-Hsing
Author_Institution
Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
Volume
26
Issue
9
fYear
1991
fDate
9/1/1991 12:00:00 AM
Firstpage
1324
Lastpage
1328
Abstract
A CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results verified the high speed and race-free performance of the proposed LCDL
Keywords
CMOS integrated circuits; VLSI; combinatorial circuits; integrated logic circuits; pipeline processing; LCDL circuits; complex combinational logic function; high-speed VLSI; latched CMOS differential logic; pipeline structure; race-free performance; CMOS logic circuits; Clocks; Logic circuits; Logic functions; MOS devices; Pipelines; Power dissipation; Switches; Very large scale integration; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.84952
Filename
84952
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