DocumentCode :
1353867
Title :
Matrix Codes for Reliable and Cost Efficient Memory Chips
Author :
Argyrides, Costas ; Pradhan, Dhiraj K. ; Kocak, Taskin
Author_Institution :
Dept. of Comput. Sci., Univ. of Bristol, Bristol, UK
Volume :
19
Issue :
3
fYear :
2011
fDate :
3/1/2011 12:00:00 AM
Firstpage :
420
Lastpage :
428
Abstract :
This paper presents a method to protect memories against multiple bit upsets and to improve manufacturing yield. The proposed method, called a Matrix code, combines Hamming and Parity codes to assure the improvement of reliability and yield of the memory chips in the presence of high defects and multiple bit-upsets. The method is evaluated using fault injection experiments. The results are compared to well-known techniques such as Reed-Muller and Hamming codes. The proposed technique performs better than the Hamming codes and achieves comparable performance with Reed-Muller codes with very favorable implementation gains such as 25% reduction in area and power consumption. It also achieves reliability increase by more than 50% in some cases. Further, the yield benefits provided by the proposed method, measured by the yield improvements per cost metric, is up to 300% better than the ones provided by Reed-Muller codes.
Keywords :
Hamming codes; Reed-Muller codes; digital storage; low-power electronics; reliability; Hamming code; Matrix codes; Parity code; Reed-Muller code; cost efficient memory chip; fault injection experiments; power consumption; reliable memory chip; Error correcting codes (ECCs); memories; reliability; yield;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2009.2036362
Filename :
5352255
Link To Document :
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