Test-set embedding based on width compression for mixed-mode BIST

Author

Chakrabarty, Krishnendu ; Das, Sunil R.

Author_Institution

Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA

Volume

49

Issue

3

fYear

2000

fDate

6/1/2000 12:00:00 AM

Firstpage

671

Lastpage

678

Abstract

We present a new test generator circuit (TGC) for mixed-mode built-in self-test (BIST) that embeds a precomputed deterministic test set T_D in a longer sequence. The design method employs width compression based on the property of d-compatibles. To demonstrate the feasibility of the TGC design methods, we present experimental data for single stuck-at test sets for the ISCAS 85 circuits and full-scan versions of the ISCAS 89 benchmark circuits. We also achieve significant improvement over another recently-proposed mixed-mode TGC design scheme for BIST

Keywords

automatic test pattern generation; built-in self test; data compression; deterministic algorithms; embedded systems; encoding; logic testing; mixed analogue-digital integrated circuits; random processes; ISCAS 85 circuits; ISCAS 89 benchmark circuits; TGC design; built-in self-test; d-compatibles; experimental data; fault coverage; feasibility; full-scan versions; mixed-mode BIST; precomputed deterministic test set; single stuck-at test sets; test generator circuit; test per clock; test-set embedding; width compression; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design methodology; Encoding; Flip-flops; Logic testing; Random sequences; Test pattern generators;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/19.850413

Filename

850413