• DocumentCode
    1354275
  • Title

    Low-Temperature Sintering of Nanoscale Silver Paste for Attaching Large-Area ({>}100~{\\rm mm}^{2}) Chips

  • Author

    Lei, Thomas Guangyin ; Calata, Jesus Noel ; Lu, Guo-Quan ; Chen, Xu ; Luo, Shufang

  • Author_Institution
    Dept. of Mater. Sci. & Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
  • Volume
    33
  • Issue
    1
  • fYear
    2010
  • fDate
    3/1/2010 12:00:00 AM
  • Firstpage
    98
  • Lastpage
    104
  • Abstract
    A low-temperature sintering technique enabled by a nanoscale silver paste has been developed for attaching large-area (>100 mm2) semiconductor chips. This development addresses the need of power device or module manufacturers who face the challenge of replacing lead-based or lead-free solders for high-temperature applications. The solder-reflow technique for attaching large chips in power electronics poses serious concern on reliability at higher junction temperatures above 125??C. Unlike the soldering process that relies on melting and solidification of solder alloys, the low-temperature sintering technique forms the joints by solid-state atomic diffusion at processing temperatures below 275??C with the sintered joints having the melting temperature of silver at 961??C. Recently, we showed that a nanoscale silver paste could be used to bond small chips at temperatures similar to soldering temperatures without any externally applied pressure. In this paper, we extend the use of the nanomaterial to attach large chips by introducing a low pressure up to 5 MPa during the densification stage. Attachment of large chips to substrates with silver, gold, and copper metallization is demonstrated. Analyses of the sintered joints by scanning acoustic imaging and electron microscopy showed that the attachment layer had a uniform microstructure with micrometer-sized porosity with the potential for high reliability under high-temperature applications.
  • Keywords
    diffusion; electron microscopy; electronics packaging; nanoelectronics; porosity; semiconductor device metallisation; silver; sintering; Ag; copper metallization; electron microscopy; low-temperature sintering; melting temperature; micrometer-sized porosity; nanoscale silver paste; power electronics; scanning acoustic imaging; semiconductor chips; solder-reflow technique; solid-state atomic diffusion; solidification; temperature 961 degC; High-temperature electronics packaging; large-area semiconductor devices; low-temperature sintering; nanoscale silver paste;
  • fLanguage
    English
  • Journal_Title
    Components and Packaging Technologies, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1521-3331
  • Type

    jour

  • DOI
    10.1109/TCAPT.2009.2021256
  • Filename
    5352309