Title :
Phase-locked loop design for on-chip tuning applications
Author :
Osa, J.I. ; Carlosena, A. ; Lopez-Martin, A.J.
Author_Institution :
Dept. of Electr. & Electron. Eng., Public Univ. of Navarra, Pamplona, Spain
fDate :
4/13/2000 12:00:00 AM
Abstract :
A novel phase-locked loop scheme is proposed, the main application of which is in on-chip tuning circuits. It involves the use of a variable gain amplifier and also a frequency tunable loop filter, providing infinite hold-in range, a fractionally constant pull-out range and also a fractionally constant ripple
Keywords :
CMOS analogue integrated circuits; circuit tuning; phase locked loops; 0.5 micron; CMOS implementation; PLL design; fractionally constant pull-out range; fractionally constant ripple; frequency tunable loop filter; infinite hold-in range; onchip tuning applications; phase-locked loop scheme; variable gain amplifier;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20000576
