DocumentCode :
1354954
Title :
A very small bipolar transistor technology with sidewall polycide base electrode for ECL-CMOS LSIs
Author :
Shiba, Takeo ; Tamaki, Yoichi ; Onai, Takahiro ; Kiyota, Yukihiro ; Kure, Tokuo ; Nakamura, Tohru
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Volume :
43
Issue :
9
fYear :
1996
fDate :
9/1/1996 12:00:00 AM
Firstpage :
1357
Lastpage :
1363
Abstract :
Very small, high-performance, silicon bipolar transistors (SPOTEC) are developed for use in ECL-CMOS LSIs. The transistors are fabricated with a sidewall polycide base; chemical vapor deposition is used to selectively deposit tungsten on the sidewall surface of the polysilicon base. The tungsten is then silicided. This self-aligned polycide technology makes a narrow (0.4-μm wide), low-resistance (7 Ω/□) base electrode possible. Narrow U-groove isolation and narrow collector metallization techniques are used to reduce the transistor area to 10 μm2. A shallow E-B junction and base layer have now been formed by using rapid-vapor-phase doping. The resulting transistors have good I-V characteristics without leakage current or high current gain. They have a high cut-off frequency of 37 GHz (53 GHz with pedestal collector ion implantation and thin epitaxial layer) and small junction capacitances. These transistors facilitate the development of very-high-speed, high-density ULSIs
Keywords :
BiCMOS integrated circuits; ULSI; bipolar transistors; chemical vapour deposition; emitter-coupled logic; integrated circuit metallisation; ion implantation; isolation technology; very high speed integrated circuits; 0.4 mum; 37 GHz; 53 GHz; ECL-CMOS LSI; I-V characteristics; SPOTEC; Si bipolar transistors; W silicidation; WSi2-Si; chemical vapor deposition; high cut-off frequency; low-resistance base electrode; narrow U-groove isolation; narrow collector metallization; pedestal collector ion implantation; rapid-vapor-phase doping; selective W deposition; shallow E-B junction; sidewall polycide base electrode; small junction capacitance; thin epitaxial layer; transistor area reduction; very small bipolar transistor technology; very-high-speed high-density ULSI; Bipolar transistors; Chemical technology; Chemical vapor deposition; Doping; Electrodes; Isolation technology; Leakage current; Metallization; Silicon; Tungsten;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.535319
Filename :
535319
Link To Document :
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