Title :
In-circuit hot-carrier model and its application to inverter chain optimization
Author :
Horiuchi, Tadahiko
Author_Institution :
ULSI Device Dev. Labs., NEC Corp., Kangawa, Japan
fDate :
9/1/1996 12:00:00 AM
Abstract :
An analytical in-circuit device lifetime model and design methodology for minimizing hot-carrier effects in an inverter chain are presented. Based on the model, in-circuit device lifetime, τAC , for hot-carrier induced degradation is given by τAC =τDC/R, R≡√π/2√Vcc/b√(T rise.Tfall)/Tc where τDC is the device lifetime under a DC test, Trise and Tfall are the rise time for input and fall time for output, TC is cycle time and b is a constant. The model also shows that minimizing circuit delay in the inverter chain maximizes hot-carrier reliability
Keywords :
CMOS logic circuits; MOSFET; circuit optimisation; delays; equivalent circuits; hot carriers; integrated circuit modelling; integrated circuit reliability; logic gates; semiconductor device models; semiconductor device reliability; CMOS inverter; circuit delay minimisation; design methodology; hot-carrier induced degradation; hot-carrier model; hot-carrier reliability; incircuit device lifetime model; inverter chain optimization; n-channel MOSFET; Circuit simulation; Degradation; Hot carrier effects; Hot carriers; Inverters; Large scale integration; MOSFETs; Semiconductor device modeling; Switching circuits; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
