Design and modeling of a new silicon-based tunneling field-effect transistor

Author

Zhang, Wei E. ; Wang, Fu-Cheng ; Yang, C.H.

Author_Institution

Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA

Volume

43

Issue

9

fYear

1996

fDate

9/1/1996 12:00:00 AM

Firstpage

1441

Lastpage

1447

Abstract

As the effective channel length of conventional MOSFET´s approaches the sub-0.1 μm regime, further downscaling of integrated circuits may require new transistor structures. In this paper we propose a new tunneling field-effect transistor. According to its new operating principle, the tunneling current between two terminals is strongly modulated by the bias applied to the third terminal. Different from the planar structure of MOSFET´s, the three terminals of this transistor are vertically stacked up. This new tunneling transistor is free of the short-channel effects, and its lateral dimension can in principle be scaled down to nanometers. The design of new transistor structure, calculated results and scaling properties are discussed

Keywords

elemental semiconductors; equivalent circuits; insulated gate field effect transistors; semiconductor device models; silicon; tunnel transistors; 0.1 micron; Si; Si-based FET; modeling; scaling properties; sub-0.1 μm channel length; tunneling field-effect transistor; vertically stacked structure; Capacitance; Degradation; Doping; Electron mobility; FET integrated circuits; Large scale integration; MOSFET circuits; Silicon; Switches; Tunneling;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.535330

Filename

535330