Design and modeling of a new silicon-based tunneling field-effect transistor

As the effective channel length of conventional MOSFET´s approaches the sub-0.1 μm regime, further downscaling of integrated circuits may require new transistor structures. In this paper we propose a new tunneling field-effect transistor. According to its new operating principle, the tunneling current between two terminals is strongly modulated by the bias applied to the third terminal. Different from the planar structure of MOSFET´s, the three terminals of this transistor are vertically stacked up. This new tunneling transistor is free of the short-channel effects, and its lateral dimension can in principle be scaled down to nanometers. The design of new transistor structure, calculated results and scaling properties are discussed