• DocumentCode
    1355654
  • Title

    Low-glitch, high-speed charge-pump circuit for spur minimisation

  • Author

    Hwang, In-Chul ; Bae, S.-G.

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Kangwon Nat. Univ., Chuncheon, South Korea
  • Volume
    45
  • Issue
    25
  • fYear
    2009
  • Firstpage
    1273
  • Lastpage
    1274
  • Abstract
    For spur reduction in RF frequency synthesisers, a simple and effective charge-pump circuit is proposed. A prototype frequency synthesiser fabricated on a 0.13 ??m CMOS process, achieves -71.32 dBc at 8.184 MHz offset from a 1.571 GHz carrier with just a second-order loop filter. When the spur level is converted to the input phase error of the PFD, it equals 0.0026 rad.
  • Keywords
    CMOS integrated circuits; charge pump circuits; frequency synthesizers; CMOS process; RF frequency synthesisers; frequency 1.571 GHz; frequency 8.184 MHz; high-speed charge-pump circuit; second-order loop filter; size 0.13 mum; spur minimisation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2009.2660
  • Filename
    5353328
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1355654