A low-power, ultra-low capacitance BICMOS process applied to a 2 GHz low-noise amplifier

Author

Van der Wel, Wim ; Koster, Ronald ; Jansen, Sander C L ; Ahlrichs, Freek W. ; Baltus, Peter G M ; Kant, Gideon W.

Author_Institution

Philips Semicond., Nijmegen, Netherlands

Volume

43

Issue

9

fYear

1996

fDate

9/1/1996 12:00:00 AM

Firstpage

1539

Lastpage

1546

Abstract

A BICMOS process is presented that includes an ultra-low capacitance NPN bipolar transistor (PRET) together with conventional 10 GHz single-poly NPN and MOS devices. Isolation is done using shallow (STI) and deep trenches. The mechanism of capacitance reduction by STI is discussed. The PRET concept, with a 0.2 μm-wide emitter is shown to yield record low capacitances (emitter/base: 1.5 fF, collector/base: 1 fF) combined with high-frequency capability (the cut-off frequency is 14 GHz). This concept is demonstrated in a 2 GHz low-noise amplifier. Proper functioning is obtained at a 3 times lower power consumption than previously reported in literature

Keywords

BiCMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; capacitance; isolation technology; mobile radio; 0.2 micron; 1 fF; 1.5 fF; 2 GHz; PRET concept; STI; capacitance reduction; cut-off frequency; deep trenches; high-frequency capability; isolation; low-noise amplifier; power consumption; shallow trenches; ultra-low capacitance BICMOS process; BiCMOS integrated circuits; Bipolar transistors; Cutoff frequency; Energy consumption; Etching; Isolation technology; Low-noise amplifiers; MOS devices; Parasitic capacitance; Substrates;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.535347

Filename

535347