DocumentCode
1356737
Title
Configurable algorithms for complete exchange in 2D meshes
Author
Suh, Young-Joo ; Yalamanchili, Sudhakar
Author_Institution
Dept. of Comput. Sci. & Eng., Pohang Inst. of Sci. & Technol., South Korea
Volume
11
Issue
4
fYear
2000
fDate
4/1/2000 12:00:00 AM
Firstpage
337
Lastpage
356
Abstract
The interprocessor complete exchange communication pattern can be found in many important parallel algorithms. In this paper, we present algorithms for complete exchange on 2D mesh-connected multiprocessors. The unique feature of the proposed algorithms is that they are configurable where the time for message startups can be traded against larger message sizes. At one extreme, the algorithm minimizes the number of message startups at the expense of an increased amount of time spent in message transmission. At the other extreme, the time spent in message transmission is reduced at the expense of an increased number of message startups. The structure of the algorithms is such that intermediate solutions are feasible, i.e., the number of message startups can be increased slightly and the message transmission time is correspondingly reduced. The ability to configure these algorithms enables the algorithm characteristics to be matched with machine characteristics based on specific overheads for message initiation and link speeds to minimize overall execution time. In effect, the algorithms can be configured to strike the right balance between direct and message combining approaches on a specific architecture for a given problem size. We believe these algorithms are distinguished by this ability and contribute to efficient portable implementations of complete exchange algorithms
Keywords
distributed memory systems; multiprocessor interconnection networks; parallel algorithms; 2D mesh-connected multiprocessors; all-to-all communication; all-to-all personalized exchange; collective communication; complete exchange; complete exchange algorithms; interprocessor communication; parallel algorithms; Broadcasting; Delay; High-speed networks; Message passing; Multiprocessor interconnection networks; Parallel algorithms; Parallel architectures; Processor scheduling; Scattering; Scheduling algorithm;
fLanguage
English
Journal_Title
Parallel and Distributed Systems, IEEE Transactions on
Publisher
ieee
ISSN
1045-9219
Type
jour
DOI
10.1109/71.850832
Filename
850832
Link To Document