• DocumentCode
    1356745
  • Title

    Cacheminer: A runtime approach to exploit cache locality on SMP

  • Author

    Yong Yan ; Xiaodong Zhang

  • Author_Institution
    Comput. Syst. Labs., Hewlett-Packard Co., Palo Alto, CA, USA
  • Volume
    11
  • Issue
    4
  • fYear
    2000
  • fDate
    4/1/2000 12:00:00 AM
  • Firstpage
    357
  • Lastpage
    374
  • Abstract
    Exploiting cache locality of parallel programs at runtime is a complementary approach to a compiler optimization. This is particularly important for those applications with dynamic memory access patterns. We propose a memory-layout oriented technique to exploit cache locality of parallel loops at runtime on Symmetric Multiprocessor (SMP) systems. Guided by application-dependent and targeted architecture-dependent hints, our system, called Cacheminer, reorganizes and partitions a parallel loop using the memory-access space of its execution. Through effective runtime transformations, our system maximizes the data reuse in each partitioned data region assigned in a cache, and minimizes the data sharing among the partitioned data regions assigned to all caches. The executions of tasks in the partitions are scheduled in an adaptive and locality-presented way to minimize the execution time of programs by trading off load balance and locality. We have implemented the Cacheminer runtime library on two commercial SMP servers and an SimCS simulated SMP. Our simulation and measurement results show that our runtime approach can achieve comparable performance with the compiler optimizations for programs with regular computation and memory-access patterns, whose load balance and cache locality can be well optimized by the tiling and other program transformations. However, our experimental results show that our approach is able to significantly improve the memory performance for the applications with irregular computation and dynamic memory access patterns. These types of programs are usually hard to optimize by static compiler optimizations
  • Keywords
    optimising compilers; parallel programming; Cacheminer; Symmetric Multiprocessor; cache locality; compiler optimization; dynamic memory access patterns; memory performance; memory-layout oriented technique; parallel programs; Adaptive scheduling; Application software; Computational modeling; Computer Society; Hardware; Network servers; Optimizing compilers; Parallel processing; Program processors; Runtime;
  • fLanguage
    English
  • Journal_Title
    Parallel and Distributed Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1045-9219
  • Type

    jour

  • DOI
    10.1109/71.850833
  • Filename
    850833