Analysis of a class of direct sampling receiver architectures from signal processing and system perspective

A class of radio frequency (RF) sampling receiver architectures has been in the focus of research in the past, as it proved to be competitive in the key performance metrics to analog RF architectures. In a first step this paper derives a generalized signal flow representation to describe this class of receivers. In a next step the parameters of the signal domain are mapped back to the circuit domain to estimate the cost of a realization. In a last step the parasitic features of a circuit representation are taken into account, resulting in an overview over the system design space that can be covered with this class of architectures. Validation of signal theoretical model to circuit representation is done by transistor level simulation in a 65 nm environment.