Design of New Logic Architectures Utilizing Optimized Suspended-Gate Single-Electron Transistors

Author

Pruvost, Benjamin ; Uchida, Ken ; Mizuta, Hiroshi ; Oda, Shunri

Author_Institution

Quantum Nanoelectron. Res. Center, Tokyo Inst. of Technol., Tokyo, Japan

Volume

9

Issue

4

fYear

2010

fDate

7/1/2010 12:00:00 AM

Firstpage

504

Lastpage

512

Abstract

The operation and performances of the suspended-gate single-electron transistor (SET) are investigated through simulation. The movable gate is 3-D optimized, so that low actuation voltage (0.4 V), fast switching (1 ns), and ultralow pull-in energy (0.015 fJ) are simulated. A two-state capacitor model based on the 3-D results is then embedded with a SET analytical model in a SPICE environment to investigate the operation of the device. Through the control of the Coulomb oscillation characteristics, the position of the movable gate enables a background charge insensitive coding of the information. New circuit architectures with applications in cellular nonlinear network and pattern matching are also proposed and simulated.

Keywords

capacitors; single electron transistors; Coulomb oscillation characteristics; SPICE environment; cellular nonlinear network; energy 0.015 fJ; logic architectures; optimized suspended-gate single-electron transistors; pattern matching; time 1 ns; two-state capacitor model; voltage 0.4 V; 1-D and 3-D modeling; cantilever switch; movable gate; nanoelectromechanical system (NEMS); single-electron transistor (SET);

fLanguage

English

Journal_Title

Nanotechnology, IEEE Transactions on

Publisher

ieee

ISSN

1536-125X

Type

jour

DOI

10.1109/TNANO.2009.2030502

Filename

5223702