NMOS source-drain extension ion implantation into heated substrates

The emergence of three-dimensional structures (Tri-gate, FinFET, etc.) in modern CMOS manufacturing have required new technologies to mitigate ion implant damage effects. Traditional beamline ion implant provides a well understood and well controlled approach to fin doping given that the pitches between source/drain fins and/or the polysilicon gates allow it without shadowing of active device structures. However, traditional beamline ion implant also causes silicon damage that can prove particularly problematic at the dimensions associated with modern 3-dimensional transistors. In this work we perform traditional beamline ion implants into silicon wafer substrates that are heated to elevated temperatures in an effort to mitigate ion implant damage effects. The net impact of damage mitigation using this technology is shown on flat wafers, topographical wafers, and finally on 22 nm NMOS trigate devices.