Title :
A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors
Author_Institution :
ConSentry Networks, Milpitas
Abstract :
Process variations in advanced nodes introduce significant core-to-core performance differences in single-chip multi-core architectures. Isolating each core with its own frequency and voltage island helps improving the performance of the multi-core architecture by operating at the highest frequency possible rather than operating all the cores at the frequency of the slowest core. However, inter-core communication suffers from additional cross-clock-domain latencies that can offset the performance benefits. This work proposes the concept of the configurable, variable-size frequency and voltage domain, and it is described in the context of a tile-based, massive multi-core architecture.
Keywords :
computer architecture; network-on-chip; cross-clock-domain latency; intercore communication; massive multicore processors; multicore architecture; network-on-chip; process-variation aware technique; single-chip multicore architectures; tile-based multicore processors; variable-size frequency domain; voltage domain; Multi-core/single-chip multiprocessors; On-chip interconnection networks;
Journal_Title :
Computer Architecture Letters
DOI :
10.1109/L-CA.2009.48
