• DocumentCode
    1358282
  • Title

    Analyze jitter to improve high-speed design

  • Author

    Lauterbach, Michael ; Wey, Todd

  • Author_Institution
    LeCroy Corp., Chestnut Ridge, NY, USA
  • Volume
    37
  • Issue
    7
  • fYear
    2000
  • fDate
    7/1/2000 12:00:00 AM
  • Firstpage
    62
  • Lastpage
    67
  • Abstract
    The authors describe how, in order to overcome timing jitter-the nemesis of high-speed design engineers-its source must be known. They detail how, to divine its source, thousands of signal observations must be collected and scrutinized to uncover flaws
  • Keywords
    high-speed integrated circuits; integrated circuit design; timing jitter; circuit flaws; design engineers; design improvement; high-speed circuit design; jitter source detection; signal observations; timing jitter; Design engineering; Timing jitter;
  • fLanguage
    English
  • Journal_Title
    Spectrum, IEEE
  • Publisher
    ieee
  • ISSN
    0018-9235
  • Type

    jour

  • DOI
    10.1109/6.852054
  • Filename
    852054
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1358282