DocumentCode
1358310
Title
A pulse-based, parallel-element macromodel for ferroelectric capacitors
Author
Sheikholeslami, Ali ; Gulak, P. Glenn ; Takauchi, Hideki ; Tamura, Hirotaka ; Yoshioka, Hiroshi ; Tamura, Tetsuro
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Volume
47
Issue
4
fYear
2000
fDate
7/1/2000 12:00:00 AM
Firstpage
784
Lastpage
791
Abstract
A pulse-based behavioral model is proposed and implemented in HSPICE. Hysteresis-loop and pulse measurement results are used to extract the model parameters. The model accurately predicts the bitline voltage of a ferroelectric memory testchip.
Keywords
SPICE; dielectric hysteresis; ferroelectric capacitors; ferroelectric storage; modelling; HSPICE; bitline voltage; ferroelectric capacitors; ferroelectric memory; hysteresis-loop; parallel-element macromodel; pulse-based behavioral model; Capacitors; Circuit simulation; Ferroelectric materials; Hysteresis; Iron; Predictive models; Pulse measurements; Space vector pulse width modulation; Switches; Voltage;
fLanguage
English
Journal_Title
Ultrasonics, Ferroelectrics, and Frequency Control, IEEE Transactions on
Publisher
ieee
ISSN
0885-3010
Type
jour
DOI
10.1109/58.852059
Filename
852059
Link To Document