• DocumentCode
    1358380
  • Title

    A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS

  • Author

    Onouchi, Masafumi ; Kanno, Yusuke ; Saen, Makoto ; Komatsu, Shigenobu ; Yasu, Yoshihiko ; Ishibashi, Koichiro

  • Author_Institution
    Central Res. Lab., Hitachi Ltd., Tokyo, Japan
  • Volume
    45
  • Issue
    11
  • fYear
    2010
  • Firstpage
    2312
  • Lastpage
    2320
  • Abstract
    Abstract-A wide-range voltage-and-frequency clock synchronizer (WRCS) for maintaining synchronization during dynamic voltage-and-frequency scaling was developed. The key feature of the WRCS is short-range skew measurement based on a predictive-delay-adjustment (PDA) scheme. The short-range skew measurement results in reduction of the area of the WRCS by 77%, that is, the area of the fabricated WRCS in a 40-nm CMOS process is only 5.65 × 10-3 mm2. In the case of large voltage variation (0.8-1.55 V) and wide frequency range (100 MHz-1 GHz), measured skew is suppressed to the lowest percentage yet reported, namely, less than 6.8% of clock period. Moreover, current consumption of the WRCS is only 0.48 mA under 1.1-V 100-MHz operation.
  • Keywords
    clocks; delay circuits; low-power electronics; power aware computing; system-on-chip; DVFS; continuous voltage scaling; current 0.48 mA; dynamic voltage-and-frequency scaling; frequency 100 MHz; low-power wide-range clock synchronizer; predictive-delay-adjustment scheme; short-range skew measurement; size 40 nm; voltage 1.1 V; Clocks; Delay; Shift registers; Synchronization; System-on-a-chip; Voltage control; Clock synchronizer; dynamic voltage-and-frequency scaling (DVFS) control; low power;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2010.2065610
  • Filename
    5607214