Title :
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
Author :
Chung, Yung-Hui ; Wu, Jieh-Tsorng
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
A 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. To reduce power consumption, the ADC uses latch-type comparators for signal digitalization and an open-loop amplifier for residue amplification. The accuracy of the comparators is improved by offset calibration. The gain accuracy and the linearity of the residue amplifier are enhanced by digital background calibration. The ADC consumes 6 mW from a 1 V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respectively. Measured ENOB is 9.34 bits. The FOM is 100 fJ·V per conversion-step.
Keywords :
CMOS integrated circuits; amplifiers; analogue-digital conversion; CMOS technology; ENOB; SFDR; SNR; analog-digital converter; complementary metal-oxide-semiconductor; digital background calibration; effective number of bits; figure of merit; gain accuracy; latch-type comparators; offset calibration; open-loop amplifier; power 6 mW; power consumption; residue amplification; residue amplifier linearity; signal digitalization; signal-noise ratio; size 90 nm; spurious-free dynamic range; storage capacity 10 bit; storage capacity 9.34 bit; two-step ADC; voltage 1 V; Accuracy; CMOS integrated circuits; Calibration; Capacitors; Clocks; Latches; Resistors; Analog-digital conversion; calibration; comparators (circuits); subranging ADC; two-step ADC;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2010.2063590
