Title :
A 29-ns 64-Mb DRAM with hierarchical array architecture
Author :
Nakamura, Masayuki ; Takahashi, Tugio ; Akiba, Takesada ; Kitsukawa, Goro ; Morino, Makoto ; Sekiguchi, Toshihiro ; Asano, Isamu ; Komatsuzaki, Katsuo ; Tadaki, Yoshitaka ; Cho, Songsu ; Kajigaya, Kazuhiko ; Tachibana, Tadashi ; Sato, Katsuyuki
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
fDate :
9/1/1996 12:00:00 AM
Abstract :
A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm 2, and the chip size is 15.91×9.06 mm2. A typical access time under 3.3 V power supply voltage is 29 ns
Keywords :
CMOS memory circuits; DRAM chips; memory architecture; 0.25 micron; 29 ns; 3.3 V; 64 Mbit; CMOS segment driver circuit; DRAM; hierarchical I/O scheme; hierarchical array architecture; hierarchical word line scheme; high speed data transfer; phase-shift optical lithography; precharge signal drivers; semidirect sensing switch; shared sense amplifier signal drivers; CMOS process; CMOS technology; Distributed amplifiers; Driver circuits; High speed optical techniques; Low voltage; Optical amplifiers; Optical switches; Random access memory; Stimulated emission;
Journal_Title :
Solid-State Circuits, IEEE Journal of
