• DocumentCode
    1359038
  • Title

    An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

  • Author

    Hsiao, Keng-Jan ; Lee, Tai-Cheng

  • Author_Institution
    Electr. Eng. Dept., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    44
  • Issue
    9
  • fYear
    2009
  • Firstpage
    2478
  • Lastpage
    2487
  • Abstract
    A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the multiphase clock generator. The high-speed multiphase clock generator produces a five-phase clock at a frequency range of 8 to 10 GHz. Additionally, the discrete-time model for the distributed DLL and the analysis about stability and noise are proposed in this work. The measured rms jitter is 293.3 fs and the maximum phase mismatch is 1.4 ps. The proposed architecture can suppress the jitter by 58%. The distributed DLL occupies 0.03 mm2 active area in a 90-nm CMOS technology and consumes 15 mA from a 1.0-V supply.
  • Keywords
    CMOS integrated circuits; MMIC; clocks; delay lock loops; CMOS technology; MMIC; current 15 mA; delay lock loops; discrete-time model; frequency 8 GHz to 10 GHz; multiphase clock generator; phase mismatch; size 90 nm; voltage 1.0 V; CMOS technology; Calibration; Capacitors; Circuits; Clocks; Delay; Frequency; Jitter; Phased arrays; Stability analysis; Clock generator; delay-locked loop; low-jitter; multiphase clock;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2009.2024804
  • Filename
    5226686