DocumentCode :
1360159
Title :
Processor scheduling and allocation for 3D torus multicomputer systems
Author :
Choo, Hyunseung ; Yoo, Seong-Moo ; Youn, Hee Yong
Author_Institution :
Dept. of Electr. & Comput. Eng., Sung Kyun Kwan Univ., Suwon, South Korea
Volume :
11
Issue :
5
fYear :
2000
fDate :
5/1/2000 12:00:00 AM
Firstpage :
475
Lastpage :
484
Abstract :
Multicomputer systems achieve high performance by utilizing a number of computing nodes. Recently, by achieving significant reductions in communication delay, the three-dimensional (3D) torus has emerged as a new candidate interconnection topology for message-passing multicomputer systems. In this paper, we propose an efficient processor allocation scheme-scan search scheme-for the 3D torus based on a first-fit approach. The scan search scheme minimizes the average allocation time for an incoming task by effectively manipulating the 3D information on a torus as 2D information using a data structure called the CST (Coverage Status Table). Comprehensive computer simulation reveals that the allocation time of the scan search scheme is always smaller than that of the earlier scheme based on a best-fit approach. The difference gets larger as the input load increases, and it is as much a factor of 3 for high load. To investigate the performance of the proposed scheme in different scheduling environments, we also consider a non-FCFS scheduling policy along with the typical FCFS policy. The allocation time complexity of the scan search scheme is O(LW2H2). This is significantly smaller than that of the existing scheme which is O(L4W4H4). Here, L, W, and H represent the length, width, and height of 3D torus, respectively
Keywords :
computational complexity; multiprocessor interconnection networks; processor scheduling; 3D torus multicomputer; data structure; interconnection topology; message-passing multicomputer; processor allocation; scan search scheme; time complexity; Computer Society; Computer simulation; Concurrent computing; Data structures; Delay; High performance computing; Hypercubes; Integrated circuit interconnections; Processor scheduling; Topology;
fLanguage :
English
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1045-9219
Type :
jour
DOI :
10.1109/71.852400
Filename :
852400
Link To Document :
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