DocumentCode
13604
Title
A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling
Author
Amaki, Takehiko ; Hashimoto, Mime ; Mitsuyama, Yukio ; Onoye, Takao
Author_Institution
Dept. of Inf. Syst. Eng., Osaka Univ., Suita, Japan
Volume
8
Issue
8
fYear
2013
fDate
Aug. 2013
Firstpage
1331
Lastpage
1342
Abstract
This paper presents a worst-case-aware design methodology for an oscillator-based true random number generator (TRNG) that produces highly random bit streams even under deterministic noise. We propose a stochastic behavior model to efficiently determine design parameters, and identify a class of deterministic noise under which the randomness gets the worst. They can be used to directly estimate the worst χ value of a poker test under deterministic noise without generating bit streams, which enables efficient exploration of design space and guarantees sufficient randomness in a hostile environment. The proposed model is validated by measuring prototype TRNGs fabricated with a 65-nm CMOS process.
Keywords
CMOS integrated circuits; oscillators; random number generation; stochastic processes; CMOS process; TRNG; deterministic noise; noise-tolerant oscillator; stochastic behavior modeling; true random number generator; worst-case-aware design methodology; Design methodology; Jitter; Markov processes; Noise; Oscillators; Standards; Jitter; Markov chain; True random number generator; stochastic model;
fLanguage
English
Journal_Title
Information Forensics and Security, IEEE Transactions on
Publisher
ieee
ISSN
1556-6013
Type
jour
DOI
10.1109/TIFS.2013.2271423
Filename
6548034
Link To Document