The future of test and DFT

Advances in design characteristics and design processes are creating significant challenges to design for testability (DFT) and test. Are DFT and test capabilities developing at a pace that will not limit the rapid growth of the very large semiconductor and computing industries that rely on their capabilities? To answer this question, we must understand the alignment between two fundamental sets of trends: growing chip design requirements and the development of EDA capabilities to address these requirements. I outline some of the design requirement trends and the specific issues they introduce, including: fault models; current handling; and test accuracy