Title :
Cost-driven ranking of memory elements for partial intrusion
Author :
Abadir, Magdy ; Kapur, Rohit
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
DFT techniques such as scan, BIST, or test point insertion intrude the circuitry for ease of testing. However, testing ease incurs increased silicon area requirements and performance penalities. The authors present a method of identifying cost-effect intermediate solutions
Keywords :
built-in self test; cost-benefit analysis; design for testability; BIST; DFT techniques; cost-driven ranking; cost-effect intermediate solutions; ease of testing; memory elements; partial intrusion; performance penalities; scan; silicon area requirements; test point insertion; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Concurrent computing; Cost function; Design for testability; Silicon; Timing;
Journal_Title :
Design & Test of Computers, IEEE
