Modeling digital systems using VHDL

VHDL is a hardware description language for delineating digital electronic systems. It arose out of the US government´s Very High Speed Integrated Circuits (VHSIC) program. During this program, the need for a standard language for describing the structure and function of integrated circuits became clear. Hence, the VHSIC Hardware Description Language (VHDL) was developed. VHDL was subsequently developed further under the auspices of the IEEE (IEEE Standard 1076). VHDL is now used worldwide as a tool for designing digital systems in many application areas. VHDL is designed to fill a number of needs in the design flow. First, it allows a description of the system´s structure. It describes how the system is decomposed into subsystems and how those subsystems are interconnected. Second, it allows the specification of the function of a system using familiar programming language forms. Third, as a result, it allows the design of a system to be simulated before being manufactured. Thus, designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping. Fourth, it allows the detailed structure of a design to be synthesized from a more abstract specification. This allows designers to concentrate more on strategic design decisions and reduces time to market