DocumentCode :
1360731
Title :
On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes
Author :
Lin, Chia-Yi ; Lin, Hsiu-Chuan ; Chen, Hung-Ming
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
18
Issue :
8
fYear :
2010
Firstpage :
1220
Lastpage :
1224
Abstract :
In modern chip designs, test strategies are becoming one of the most important issues due to the increase of the test cost, among them we focus on the large test power dissipation and large test data volume. In this paper, we develop a methodology to suppress the test power to avoid chip failures caused by large test power, and our methodology is also effective in reducing the test data volume and shift-in power. The proposed schemes and techniques are based on the selective test pattern compression, they can reduce considerable shift-in power by skipping the switching signal passing through long scan chains. The experimental results with ISCAS89 circuits demonstrate that our methodology can achieve significant improvement in the reduction of shift-in power and test data volume. Our approach also supports multiple scan chains.
Keywords :
integrated circuit design; integrated circuit testing; chip design; chip failure; large test data volume; large test power dissipation; selective pattern compression; selective test pattern compression; test strategies; test volume; Compression; DFT; low power; scan chain; test data volume;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2009.2021061
Filename :
5229137
Link To Document :
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