A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 $\mu$ m CMOS

An all-digital PLL for wireline applications is designed with a sub-exponent TDC which adaptively scales its resolution according to input time difference. By cascading 2× time amplifiers, the TDC efficiently generates the exponent-only information for fractional time difference. To improve linearity in a wide input range, a replica-based self-calibration scheme is applied to the time amplifier. The TDC, implemented in a 0.18 μm CMOS, shows the minimum resolution of 1.25 ps with a total conversion range of 2.5 ns, the maximum operating frequency of 250 MHz, and power consumption of 1.8 mW at 60 MHz. The measured rms jitter of PLL was 5.03 ps at 960 MHz.