Analysis and design of power efficient class D amplifier output stages

Author

Chang, Joseph S. ; Tan, Meng-Tong ; Cheng, Zhihong ; Tong, Yit-Chow

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore

Volume

47

Issue

6

fYear

2000

fDate

6/1/2000 12:00:00 AM

Firstpage

897

Lastpage

902

Abstract

A Class D amplifier comprises a pulse width modulator and an output stage. In this paper we analyze the power dissipation mechanisms and derive the overall power efficiency of the output stage realized using the finger and waffle layouts. We compare the relative merits of these layouts; we propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency (optimum for a given fabrication process, supply voltage and load resistance): (1) optimization to a single modulation index point and (2) optimization to a range of modulation indexes. For the design of an output stage with optimum power efficiency (and small IC area), we recommend optimization to a range of modulation indexes and a layout realized by the waffle structure. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype ICs

Keywords

bridge circuits; circuit optimisation; power amplifiers; pulse width modulation; aspect ratios; design methodologies; finger layout; optimum power efficiency; output stages; overall power efficiency; power dissipation mechanisms; power efficient class D amplifier; pulse width modulator; single modulation index point; waffle layout; Design methodology; Design optimization; Fabrication; Fingers; Power amplifiers; Power dissipation; Pulse amplifiers; Pulse width modulation; Space vector pulse width modulation; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.852942

Filename

852942