• DocumentCode
    1360865
  • Title

    Estimating the speedup in parallel parsing

  • Author

    Sarkar, Dilip ; Deo, Narsingh

  • Author_Institution
    Dept. of Math. & Comput. Sci., Miami Univ., Coral Gables, FL, USA
  • Volume
    16
  • Issue
    7
  • fYear
    1990
  • fDate
    7/1/1990 12:00:00 AM
  • Firstpage
    677
  • Lastpage
    683
  • Abstract
    A method for estimating the speedup for asynchronous bottom-up parallel parsing is presented. Two models for bottom-up parallel parsing are proposed, and the speedup for each of the two models is estimated. The speedup obtained for model A is a very close to the simulation result already available in literature; however, the model is restrictive because it can only communicate with its immediate left and right neighbors. This increases the processor coordination and interprocessor communication times. Model B, while showing a greater speedup time, is expensive to construct when the number of processors is large
  • Keywords
    grammars; parallel algorithms; program compilers; asynchronous bottom-up; interprocessor communication; models; parallel parsing; processor coordination; simulation result; speedup estimation; Arithmetic; Computational modeling; Computer architecture; Computer science; Mathematics; Operating systems; Parallel machines; Parallel processing; Parallel programming; Pipelines;
  • fLanguage
    English
  • Journal_Title
    Software Engineering, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-5589
  • Type

    jour

  • DOI
    10.1109/32.56094
  • Filename
    56094