DocumentCode :
1361489
Title :
A thorough study of quasi-breakdown phenomenon of thin gate oxide in dual-gate CMOSFET´s
Author :
Guan, Hao ; Li, Ming-Fu ; He, Yandong ; Cho, Byung Jin ; Dong, Zhong
Author_Institution :
Dept. of Electr. Eng., Nat. Univ. of Singapore, Singapore
Volume :
47
Issue :
8
fYear :
2000
fDate :
8/1/2000 12:00:00 AM
Firstpage :
1608
Lastpage :
1616
Abstract :
The conduction mechanism of the quasibreakdown (QB) mode for thin gate oxide has been studied in a dual-gate CMOSFET with a 3.7 nm thick gate oxide. Systematic carrier separation experiments were conducted to investigate the evolutions of gate, source/drain, and substrate currents before and after gate oxide quasibreakdown (QB). Our experimental results clearly show that QB is due to the formation of a local physically-damaged-region (LPDR) at Si-SiO2 interface. At this region, the effective oxide thickness is reduced to the direct tunneling (DT) regime. The observed high gate leakage current is due to DT electron or hole currents through the region where the LPDR is generated. Twelve Vg, Isub, Isd/ versus time curves and forty eight I-V curves of carrier separation measurements have been demonstrated. All the curves can be explained in a unified way by the LPDR QB model and the proper interpretation of the carrier separation measurements. Particularly, under substrate injection stress condition, there is several orders of magnitude increase of Isub(Isd/) at the onset point of QB for n(p)-MOSFET, which mainly corresponds to valence electrons DT from the substrate to the gate, consequently, cold holes are left in the substrate and measured as substrate current. These cold holes have no contribution to the oxide breakdown and thus the lifetime of oxide after QB is very long. Under the gate injection stress condition, there is sudden drop and even change of sign of Isub(Isd/) at the onset point of QB for n(p)-MOSFET, which corresponds to the disappearance of impact ionization and the appearance of hole DT current from the substrate to the gate
Keywords :
CMOS integrated circuits; MOSFET; ULSI; dielectric thin films; integrated circuit reliability; leakage currents; semiconductor device breakdown; semiconductor device reliability; semiconductor-insulator boundaries; tunnelling; 3.7 nm; I-V curves; Si-SiO2; Si-SiO2 interface; carrier separation experiments; direct tunneling regime; dual-gate CMOSFET; gate current; gate leakage current; gate oxide quasibreakdown; local physically-damaged-region; quasi-breakdown phenomenon; quasibreakdown model; source/drain current; substrate current; substrate injection stress condition; thin gate oxide; valence electrons; CMOSFETs; Charge carrier processes; Current measurement; Electric breakdown; Impact ionization; Leakage current; Particle measurements; Stress measurement; Time measurement; Tunneling;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.853038
Filename :
853038
Link To Document :
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