Modeling of stochastic BTI in small area devices and its impact on SRAM performance

A comprehensive framework is developed to simulate device-level variability due to process variations and Bias Temperature Instability (BTI), and study the impact on circuits such as the SRAM cell. Stochastic simulation approach consisting of the stochastic Reaction Diffusion (RD) model for interface trap generation and stochastic two energy well model for charging of pre-existing bulk traps along with either simple exponential impact assumption or complete 3D TCAD simulation, is used to generate threshold voltage and threshold voltage shift distributions. A compact model approach to generate the threshold voltage distributions from the mean compact model through a procedure that exploits experimental relationship between mean and variance of threshold voltage shift distribution is described. The impact of device-level variability on the 6T-SRAM cell read and write operations is investigated.