Influence of high temperature on substrate effect of UTBB SOI nMOSFETs

Author

Itocazu, Vitor T. ; Sonnenberg, Victor ; Simoen, Eddy ; Claeys, Cor ; Martino, Joao Antonio

Author_Institution

LSI/PSI, Univ. of Sao Paulo, Sao Paulo, Brazil

fYear

2014

fDate

1-5 Sept. 2014

Firstpage

1

Lastpage

6

Abstract

An analysis of the temperature influence on the substrate effect of short channel Ultra Thin Body and BOX (UTBB) SOI nMOSFETs with and without Ground Plane (GP) implantation is presented. This study was done from room temperature up to 200°C. The theoretical model was applied and the results are in agreement with experimental and simulation data. The data shows a kink in the drain current as a function of back-gate voltage due to the substrate potential drop when the ground plane is not present. The ground plane reduces the substrate potential drop, but increases the potential drop over the gate and buried oxides. The maximum difference between V_GB with and without GP decreases for high temperature.

Keywords

MOSFET; ion implantation; silicon-on-insulator; GP; UTBB SOI nMOSFETs; back-gate voltage function; drain current; ground plane implantation; high temperature; short channel ultra thin body and box SOI nMOSFETs; substrate effect; substrate potential drop; Bismuth; Logic gates; MOSFET; Silicon; Substrates; Ground Plane; SOI; Threshold voltage; Ultra Thin Body and Buried Oxide; simulation; substrate effect;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics Technology and Devices (SBMicro), 2014 29th Symposium on

Conference_Location

Aracaju

Type

conf

DOI

10.1109/SBMicro.2014.6940132

Filename

6940132