Title :
A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits
Author :
Iwata, Kenichi ; Irita, Takahiro ; Mochizuki, Seiji ; Ueda, Hiroshi ; Ehama, Masakazu ; Kimura, Motoki ; Takemura, Jun ; Matsumoto, Keiji ; Yamamoto, Eiji ; Teranuma, Tadashi ; Takakubo, Katsuji ; Watanabe, Hiromi ; Yoshioka, Shinichi ; Hattori, Toshihiro
Author_Institution :
Renesas Technol. Corp., Kodaira, Japan
Abstract :
A full-HD (1080p30) 500 MHz mobile application processor with an H.264 HP/MPEG-2/MPEG-4 video codec is integrated on a 6.4 × 6.5 mm2 die in 65 nm low-power CMOS. With two parallel pipelines for macroblock processing and tile-based address translation circuits, the processor consumes 342 mW in real-time playback of a full-HD H.264 stream from a 64 b width low-power DDR-SDRAM at an operating frequency of 166 MHz at 1.2 V.
Keywords :
CMOS integrated circuits; DRAM chips; coprocessors; high definition television; low-power electronics; mobile computing; video codecs; video streaming; H.264 HP/MPEG-2/MPEG-4 video codec; frequency 166 MHz; frequency 500 MHz; full-HD H.264 stream; full-HD multistandard video codec; low-power CMOS; low-power DDR-SDRAM; macroblock processing; mobile application processor; parallel pipelines; power 342 mW; size 65 nm; tile-based address translation circuits; tile-based address-translation circuits; voltage 1.2 V; Bandwidth; CMOS process; Cellular phones; Circuits; Energy consumption; High definition video; MPEG 4 Standard; Mobile handsets; Telephone sets; Video codecs; Address translation; application processor; dynamic clock control; full HD video; memory bandwidth; mobile phone; video codec;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2031797
