DocumentCode
1362856
Title
Modeling and Performance Characterization of Double-Walled Carbon Nanotube Array Field-Effect Transistors
Author
Huang, Jun Zh ; Yin, Wen-Yan
Author_Institution
Key Lab. of Design & EMC of High-Speed Electron. Syst. of Educ. Minist., Shanghai Jiao Tong Univ., Shanghai, China
Volume
58
Issue
1
fYear
2011
Firstpage
17
Lastpage
25
Abstract
The performance prediction of double-walled carbon nanotube (DWCNT) array-built field-effect transistors (DWCNTFETs) is performed theoretically. The charge densities and surface potentials of double walls are solved in a self-consistent manner with the effects of wall screening among the DWCNT array treated appropriately. Some comparisons are made between our method and the nonequilibrium Green´s function approach, with good agreement obtained. The influences of phonon scattering, doping resistances, Schottky barrier resistances, screening effects, and parasitic capacitances on DWCNTFET performance are examined in detail for different array geometries. It is found that, although its intrinsic channel part has no speed advantage over the single-walled counterpart, the overall speed performance can be better with low array densities and large diameters of the DWCNTs. The delay and cutoff frequency of the DWCNTFET can be decreased by 15% and increased by 30%, respectively. In particular, its better on current property can be utilized in the design of nanodevices with high-power-handling capability.
Keywords
Schottky barriers; carbon nanotubes; field effect transistors; nanotube devices; C; Schottky barrier resistances; charge densities; doping resistances; double walled carbon nanotube array; field effect transistors; parasitic capacitances; performance characterization; phonon scattering; screening effects; self-consistent manner; surface potentials; Arrays; Integrated circuit modeling; Logic gates; Mathematical model; Metals; Quantum capacitance; Carbon nanotube field-effect transistor (FET) (CNTFET); cutoff frequency; double-walled carbon nanotube (DWCNT); lumped-element circuit model; on current; signal delay;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2010.2082547
Filename
5611587
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