• DocumentCode
    1363190
  • Title

    A parallel algorithm for allocation of spare cells on memory chips

  • Author

    Funabiki, Nobuo ; Takefuji, Yoshiyasu

  • Author_Institution
    Case Western Reserve Univ., Cleveland, OH, USA
  • Volume
    40
  • Issue
    3
  • fYear
    1991
  • fDate
    8/1/1991 12:00:00 AM
  • Firstpage
    338
  • Lastpage
    346
  • Abstract
    The authors propose a parallel algorithm based on the artificial neural network model for solving the spare-allocation problem. The goal is to find a spare allocation which repairs all the faulty cells in the given faulty-cell map. The parallel algorithm requires 2n processing elements for the n×n faulty-cell map problem. The algorithm is verified by many simulation runs. Under the simulation the algorithm finds one of the near-optimum solutions in a nearly constant time with O(n) processors. The simulation results show the consistency of this algorithm. The algorithm can be easily extended for solving rectangular or other shapes of fault map problems
  • Keywords
    automatic testing; computational complexity; integrated circuit testing; integrated memory circuits; neural nets; parallel algorithms; production testing; redundancy; resource allocation; storage allocation; artificial neural network model; faulty cell repair; faulty-cell map; memory chips; parallel algorithm; spare cells allocation; Artificial neural networks; Hysteresis; Manufacturing; Neurons; Parallel algorithms; Parallel processing; Polynomials; Production; Random access memory; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Reliability, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9529
  • Type

    jour

  • DOI
    10.1109/24.85454
  • Filename
    85454