Title :
A queueing network model for semiconductor manufacturing
Author :
Connors, Daniel P. ; Feigin, Gerald E. ; Yao, David D.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
8/1/1996 12:00:00 AM
Abstract :
We develop an open queueing network model for rapid performance analysis of semiconductor manufacturing facilities. While the use of queueing models for performance evaluation of manufacturing systems is not new, our approach differs from others in the detailed ways in which we model the different tool groups found in semiconductor wafer fabrication, as well as the way in which we characterize the effect of rework and scrap on wafer lot sizes. As an application of the model, we describe a method for performing tool planning for semiconductor lines. The method is based on a marginal allocation procedure which uses performance estimates from the queueing network model to determine the number of tools needed to achieve a target cycle time, with the objective being to minimize overall equipment cost
Keywords :
queueing theory; semiconductor device manufacture; semiconductor process modelling; cycle time; equipment cost minimization; lot size; marginal allocation; performance analysis; planning; production line; queueing network model; rework; scrap; semiconductor manufacturing; tool group; wafer fabrication; Computational modeling; Computer simulation; Electric breakdown; Fabrication; Manufacturing processes; Performance analysis; Queueing analysis; Semiconductor device manufacture; Semiconductor device modeling; Virtual manufacturing;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on