A statistical methodology as applied to a 256 Mbit DRAM pass transistor design

We present a novel design for manufacturing (DFM) methodology that has been applied to the design of a pass transistor for 256 Mbit DRAM. The design inputs that include gate oxide thickness, which limits the booted wordline voltage, the threshold voltage adjust implant, and the substrate bias voltage, for different channel lengths, are optimized to meet the constraints on performance, reliability, and robustness against manufacturing variations. The problems associated with applying conventional DFM techniques are discussed and a new methodology based on “margins” is presented. The results pertaining to the optimized DRAM pass transistor design for a power supply voltage V_cc=2.5 V are presented,