• DocumentCode
    1364119
  • Title

    A unified yield model incorporating both defect and parametric effects

  • Author

    Berglund, C.Neil

  • Author_Institution
    Oregon Graduate Inst. of Sci. & Technol., Portland, OR, USA
  • Volume
    9
  • Issue
    3
  • fYear
    1996
  • fDate
    8/1/1996 12:00:00 AM
  • Firstpage
    447
  • Lastpage
    454
  • Abstract
    A new approach to modeling yield is presented, which inherently includes both the effects of the conventional defect contributors and the parametric yield loss contributors often treated separately in existing yield models. These parametric yield losses are particularly important during the startup yield-improvement phase of new technology introduction, in many performance-sensitive products such as analog devices and high-speed digital devices, and in analyses of bin-split yields. By assuming a distribution in the size of defects, from point defects up to defects as large as or larger than a wafer, the parametric yield contributors can be viewed as simply rather large, design-dependent defects, which will render IC´s unacceptable if any portion of the large defect overlaps the defect-sensitive area of a chip. In this way, the conventional Poisson model, or various extensions of the well-known Murphy model, can be augmented in a straightforward and general way to include parametric yield loss. It is shown that parametric yield losses introduce an additional die size dependence for yield that can help to account for the observed dependence of yield on die area. The model is compared to other models and to experimental yield data to illustrate both its utility in separating yield contributors and its close agreement with experimental yield data
  • Keywords
    integrated circuit yield; semiconductor process modelling; IC yield model; Murphy model; Poisson model; analog device; bin-split yield; defect size distribution; high-speed digital device; parametric yield loss; startup phase; Atmospheric modeling; Integrated circuit modeling; Integrated circuit yield; Performance analysis; Semiconductor device modeling;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/66.536115
  • Filename
    536115