DocumentCode
1365071
Title
A programmable deflection processor
Author
Murakami, K. ; Miyazaki, S. ; Tamura, T. ; Murayama, H. ; Mito, Y. ; Shirahama, A.
Author_Institution
Sony Corp., Tokyo, Japan
Volume
37
Issue
3
fYear
1991
fDate
8/1/1991 12:00:00 AM
Firstpage
544
Lastpage
554
Abstract
A multi-standard vertical deflection processor which utilizes both microprocessing and digital signal processing blocks was developed. Minimal deflection distortion for large screen use and excellent vertical synchronization are achieved. This architecture can also achieve quick and reliable identification of the TV standard used and IDTV (improved definition TV) processing and non-interlace processing without additional circuits
Keywords
colour television receivers; computerised picture processing; digital signal processing chips; high definition television; microprocessor chips; IDTV; TV receiver; TV standard; colour TV; digital signal processing blocks; microprocessing block; multistandard vertical deflection processor; programmable deflection processor; vertical synchronization; Computer peripherals; Digital signal processing; HDTV; Hardware; Logic; Signal generators; Signal processing; Stability; TV receivers; Video recording;
fLanguage
English
Journal_Title
Consumer Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0098-3063
Type
jour
DOI
10.1109/30.85565
Filename
85565
Link To Document