VLSI systems design of 51.84 Mb/s transceivers for ATM-LAN and broadband access

We present: (1) system design issues for the implementation of 51.84 Mb/s ATM-LAN and broadband access transceivers and (2) a pipelined fractionally spaced linear equalizer (FSLE) architecture. Signal-to-noise ratio (SNR) and bit-error rate (BER) along with VLSI constraints are addressed. For the LAN environment, major channel impairments include near-end crosstalk (NEXT), intersymbol interference (ISI), and impulse noise. The broadband access environment suffers from far end crosstalk (FEXT), ISI, radio-frequency interference (RFI), impulse noise, and splitter losses. Measured characteristics of the channel are compared with analytical models. These are employed in the design of the transmitter/receiver algorithms. The carrierless amplitude/phase (CAP) transmission scheme is presented as a practical bandwidth-efficient scheme for these applications. An adaptive FSLE employed in a CAP receiver eliminates ISI, suppresses NEXT (for ATM-LAN) and FEXT (for broadband access), and provides robustness to timing jitter. However, fractional tap spacing in combination with the high-data rates results in a high sample rate adaptive computation. Fortunately, throughput enhancing methods such as pipelining can be used for high-speed/low-power operation. A hardware-efficient pipelined architecture for the adaptive FSLE equalizer is presented. This has been developed using relaxed look-ahead, which maintains the algorithm functionality rather than the input-output mapping. Simulation and experimental results for high-speed digital CAP transceivers for LAN and broadband access are also presented