DocumentCode :
1365690
Title :
Low power design for MPEG-2 video decoder
Author :
Lin, Chia-Hsing ; Chen, Chen-Min ; Jen, Chein-Wei
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
42
Issue :
3
fYear :
1996
fDate :
8/1/1996 12:00:00 AM
Firstpage :
513
Lastpage :
521
Abstract :
The I/O power consumption in an MPEG-2 decoder is significant because of the wide connection with large capacitances to the frame buffer. To reduce the power dissipation on the memory bus, the Gray code encoding scheme is proposed to increase the correlation of the image data transferred on the bus. The bit switching probability in the re-coded data will then decrease and in turn the bus power consumption will be reduced. Combined with the proposed bus arbitration and scheduling scheme proposed in this paper, 22% reduction of power dissipation may be achieved
Keywords :
Gray codes; VLSI; decoding; digital signal processing chips; probability; scheduling; system buses; telecommunication standards; video signal processing; Gray code; I/O power consumption; MPEG-2 video decoder; bit switching probability; bus arbitration; bus power consumption; capacitances; correlation; frame buffer; image data; low power design; memory bus; power dissipation; re-coded data; scheduling scheme; Capacitance; Circuits; Control systems; Costs; Decoding; Energy consumption; Power dissipation; Random access memory; Reflective binary codes; Very large scale integration;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/30.536150
Filename :
536150
Link To Document :
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