Title :
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network
Author :
Liu, Chih-Hao ; Lin, Chien-Ching ; Yen, Shau-Wei ; Chen, Chih-Lung ; Chang, Hsie-Chia ; Lee, Chen-Yi ; Hsu, Yar-Sun ; Shyh-Jye Jou
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22- mm2 QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.
Keywords :
CMOS integrated circuits; decoding; message passing; parity check codes; telecommunication network routing; wireless LAN; CMOS process; IEEE 802.11n; IEEE 802.16e; codeword streams; hardware complexity; message transportation; multimode QC-LDPC decoder; multimode quasi-cyclic low-density parity-check codes; postlayout simulation; reconfigurable message-passing network; shift-routing network; Architecture; IEEE 802.11n; IEEE 802.16e; WiMax; message passing; network; quasi-cyclic low-density parity check (QC-LDPC);
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2009.2027967
