Title :
A novel video signal processor with programmable data arrangement and efficient memory configuration
Author :
Lai, Yeong-Kang ; Chen, Liang-Gee ; Chen, Hsu-Tung ; Chen, Mei-Juan ; Lee, Yung-Pin ; Wu, Po-Cheng
Author_Institution :
Nat. Taiwan Univ., Taipei, Taiwan
fDate :
8/1/1996 12:00:00 AM
Abstract :
This paper describes a novel video signal processor (VSP) with a fully pipelined parallel architecture for video browsing, coding, and image processing for multimedia systems. The efficiency of the architecture developed is increased by use of a programmable data arrangement and an intelligent memory configuration. Techniques for reducing the interconnections and external memory accesses are also presented. A configuration of random-access on-chip memory modules solves the problems of chip I/O and memory bandwidth requirement. Due to the properties of low cost, high speed, and low memory bandwidth requirements, the VSP provides efficient solutions for video signal processing applications
Keywords :
VLSI; digital signal processing chips; multimedia communication; parallel architectures; pipeline processing; random-access storage; video coding; VLSI; architecture efficiency; high speed processor; image processing; intelligent memory configuration; low cost processor; low memory bandwidth requirements; memory configuration; multimedia systems; pipelined parallel architecture; programmable data arrangement; random access onchip memory modules; video browsing; video coding; video signal processor; Bandwidth; Discrete cosine transforms; Image coding; Image processing; Multimedia systems; Signal processing; Signal processing algorithms; Transform coding; Video coding; Video signal processing;
Journal_Title :
Consumer Electronics, IEEE Transactions on
